Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to a redistribution layer for fabrication of a fan out structure.
Background
The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. The front-end-of-line processes may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The middle-of-line process may include gate contact formation. Middle-of-line layers may include, but are not limited to, middle-of-line contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The back-end-of-line processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the front-end-of-line and middle-of-line processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.
An interposer is a die-mounting technology in which the interposer serves as a base upon which the semiconductor dies of a system on chip (SoC) are mounted. An interposer is an example of a fan out wafer level package structure. The interposer may include wiring layers of conductive traces and conductive vias for routing electrical connections between the semiconductor dies (e.g., memory modules and processors) and a system board. The interposer may include a redistribution layer (RDL) that provides a connection pattern of bond pads on the active surface of a semiconductor device (e.g., a die or chip) to a redistributed connection pattern that is more suitable for connection to the system board.
Fabrication of wafer level package structures may include attachment of a semiconductor device (e.g., a die or chip) to the wafer level package structure according to a chip first attach process prior to forming the redistribution layer. The chip first attach process, however, may be problematic for split die applications, rendering the semiconductor device defective because of the formation of the redistribution layer and/or because of defects associated with the redistribution layer.